Memory circuit having data lines selectively coupled to a sense amplifier and method for operating the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 30, 2018
Issued Date -
N/A
app pub date -
Nov 2, 2015
filing date -
Sep 22, 2009
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory circuit includes a memory cell, a first bit line, a first bit line bar, a sense amplifier, a first switch and a second switch. The memory cell is coupled with a first bit line having a first bit line portion and a second bit line portion. The first bit line bar has a first bit line bar portion and a second bit line bar portion. The sense amplifier includes a read/write circuit configured to couple the second bit line portion to a global bit line. The first switch is coupled between the first bit line bar portion and the second bit line bar portion. The second switch is coupled between the first bit line portion and the second bit line portion.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2015 Application Filing Year
- G11C Class
- 4029 Applications Filed
- 3679 Patents Issued To-Date
- 91.32 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- G11C Class
- 17.97 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 30, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 30, 2029 |
