Gate drive circuit and display device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 30, 2018
Issued Date -
N/A
app pub date -
Mar 13, 2015
filing date -
Nov 28, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An embodiment of the present invention discloses a gate drive circuit comprising several stages of unit circuits, wherein each unit circuit comprises: a high level terminal, a low level terminal, a first clock terminal, a second clock terminal, a gate output terminal, a logic turn-on input terminal, a logic turn-on output terminal, a control module, a first gating module and a second gating module. An embodiment of the present invention also provides a display device comprising the gate drive circuit. A gate drive circuit with interlaced output is realized, ensuring no suspended state in time sequence between interlaced lines, while maintaining an original dual time sequence (i.e., eliminating suspended state between interlaced lines, and ensuring a stable output of the shifting register).
First Claim
Other Claims data not available
Family
International Classification(s)
- 2015 Application Filing Year
- G09G Class
- 5016 Applications Filed
- 4052 Patents Issued To-Date
- 80.79 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- G09G Class
- 0 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 30, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 30, 2029 |
