Shift register circuit, its driving method, array substrate and display device
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United States of America Patent
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Jan 30, 2018
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N/A
app pub date -
Aug 11, 2016
filing date -
Jan 5, 2016
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Abstract
The present disclosure provides a shift register circuit, which includes a first switch unit connecting an input end to a first node when a positive-phase clock signal is at a first level; a second switch unit applying a negative-phase clock signal to an output end when the first node is at the first level; a positive feedback unit enabling the second node to be at a second level when the first node is at the first level and enabling the first node to be at the second level when the second node is at the first level; a third switch unit enabling a third node to be at the first level when the positive-phase clock signal is at the first level; a fourth switch unit connecting the second node to the third node when the negative-phase clock signal is at the first level; and a fifth switch unit.
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