Overlay sampling reduction
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United States of America Patent
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Jan 30, 2018
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app pub date -
Mar 30, 2016
filing date -
Mar 30, 2016
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Abstract
Method and apparatus for reducing overlay measurements and predicting overlay in unmeasured regions of a wafer are provided. Embodiments include providing a wafer having sets of four fields sharing a common vertex; measuring overlay values near each corner of each field, except for a corner near the common vertex of a first field and a corner near the common vertex of a second field of each set; decomposing the measured overlay values into measured interfield and intrafield correctable and non-correctable errors; forming a virtual stack of all fields; determining an average intrafield correctable error and intrafield non-correctable error for each corner of the virtual stack based on the measured intrafield correctable and non-correctable errors, respectively; and predicting the overlay values for the unmeasured corners of each set based on combinations of the measured interfield correctable and non-correctable errors and the average intrafield correctable and non-correctable errors.
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