Variable frame length virtual GPIO with a modified UART interface
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United States of America Patent
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Jan 30, 2018
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N/A
app pub date -
Sep 10, 2015
filing date -
Sep 11, 2014
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Abstract
A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.
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