Bus access controller, hardware engine, controller, and memory system
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United States of America Patent
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Jan 30, 2018
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N/A
app pub date -
May 15, 2015
filing date -
Jan 15, 2015
priority date (Note) -
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Abstract
According to one embodiment, there is provided a bus access controller including a memory, multiple buffers, and an issuance circuit. Information necessary for bus access can be set in the memory. The multiple buffers store information set in the memory. The issuance circuit is connected to a bus. The issuance circuit issues a bus-access instruction, according to information stored in a buffer selected from among the multiple buffers in response to a request.
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