Cross clock compensation between layers in peripheral component interconnect express
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 30, 2018
Issued Date -
N/A
app pub date -
Dec 11, 2015
filing date -
Dec 11, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A PCIe bus adapted for cross clock compensation of asynchronous clocks includes one or more PHY data ports provided in a PHY layer having a transmit clock (TCLK) for timing data transmitted to a peripheral device and a receive clock (RCLK) for timing data received from the peripheral device, one or more media access control (MAC) ports provided in a MAC layer having an interface clock (PCLK) for timing data transmitted to the PHY layer and data received from the PHY layer, wherein the PCLK and one or both of the TCLK and the RCLK are asynchronous, and one or more backpressure ports at an interface between the PHY layer and the MAC layer for controlling reading and writing of one of the PHY layer and the MAC layer. In some aspects, the PCLK frequency is set to be always greater than a maximum frequency of the RCLK and the TCLK.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully