Dynamic set associative cache apparatus for processor and access method thereof
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United States of America Patent
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Jan 30, 2018
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N/A
app pub date -
Jul 10, 2014
filing date -
May 2, 2012
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Abstract
The present invention provides a dynamic set associative cache apparatus for a processor. When read access occurs, the apparatus first determines a valid/invalid bit of each cache block in a cache set to be accessed, and sets, according to the valid/invalid bit of each cache block, an enable/disable bit of a cache way in which the cache block is located; then, reads valid cache blocks, compares a tag section in a memory address with a tag block in each cache block that is read, and if there is a hit, reads data from a data block in a hit cache block according to an offset section of the memory address.
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