Efficient data transfer between a processor core and an accelerator
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United States of America Patent
Stats
-
Jan 30, 2018
Issued Date -
N/A
app pub date -
Mar 24, 2014
filing date -
Mar 24, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.
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- G06F Class
- 0 % this patent is cited more than
- 7 Age
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| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 30, 2025 |
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