Serial bus DRAM error correction event notification
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United States of America Patent
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Jan 30, 2018
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N/A
app pub date -
Nov 17, 2016
filing date -
May 15, 2014
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Abstract
A memory device incorporates a serial data bus coupled to the control circuit of the memory device to provide direct access to the error correction control circuit and to the error correction event notification information and error correction function configuration information stored in mode registers of the control circuit. The serial data bus enables access to the error correction control functions and to the error correction event notification information without requiring modifications to the memory controller used to control and communicate with the memory device.
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