Instruction that performs a scatter write
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United States of America Patent
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Jan 30, 2018
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N/A
app pub date -
Apr 24, 2014
filing date -
Apr 24, 2014
priority date (Note) -
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Abstract
A processor is described having an instruction execution pipeline. The instruction execution pipeline has an instruction fetch stage to fetch an instruction specifying multiple target resultant registers. The instruction execution pipeline has an instruction decode stage to decode the instruction. The instruction execution pipeline has a functional unit to prepare resultant content specific to each of the multiple target resultant registers. The instruction execution pipeline has a write-back stage to write back said resultant content specific to each of said multiple target resultant registers.
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