Data routing and buffering in a processing system
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United States of America Patent
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Jan 30, 2018
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app pub date -
Feb 5, 2016
filing date -
Feb 5, 2016
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Abstract
In a computing system where an incoming packet can be written directly into one or more local registers of a processing unit, a packet interface routes packets arriving at a computing system to the local registers of the processing unit or to a memory shared by multiple processing units. The shared memory includes a portion configured as a first-in, first-out (FIFO) buffer for storing packets arriving for the processing unit when its local registers are full. The stored packets are then delivered to the processing unit's one or more registers when the registers become available.
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