Wrap around silicide for FinFETs
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 23, 2018
Issued Date -
N/A
app pub date -
Jul 27, 2016
filing date -
Jun 15, 2015
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
First Claim
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International Classification(s)
- 2016 Application Filing Year
- H01L Class
- 27971 Applications Filed
- 23507 Patents Issued To-Date
- 84.05 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 3 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 23, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 23, 2029 |
