Wrap around silicide for FinFETs
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United States of America Patent
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Jan 23, 2018
Issued Date -
N/A
app pub date -
Jul 27, 2016
filing date -
Jun 15, 2015
priority date (Note) -
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Abstract
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
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