Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices
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United States of America Patent
Stats
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Jan 23, 2018
Issued Date -
N/A
app pub date -
Jun 30, 2016
filing date -
Jun 30, 2016
priority date (Note) -
In Force
status (Latency Note)
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Abstract
One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.
First Claim
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International Classification(s)
- 2016 Application Filing Year
- H01L Class
- 27971 Applications Filed
- 23507 Patents Issued To-Date
- 84.05 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 4 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
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| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 23, 2025 |
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