TFT arrangement structure
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United States of America Patent
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Jan 23, 2018
Issued Date -
N/A
app pub date -
May 21, 2015
filing date -
Apr 14, 2015
priority date (Note) -
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Abstract
The present invention provides a TFT arrangement structure, comprising a first thin film transistor (T1) and a second thin film transistor (T2) controlled by the same control signal line; the first active layer (SC1) of the first thin film transistor (T1) and the second active layer (SC2) of the second thin film transistor (T2) are at different layers, and positioned to stack up in space, and the first source (S1) and the first drain (D1) of the first thin film transistor (T1) are formed on the first active layer (SC1), and the second source (S2) and the second drain (D2) of the second thin film transistor (T2) are formed on the second active layer (SC2); the gate layer (Gate) is electrically coupled to the control signal line to control on and off of the first, the second thin film transistors (T1, T2). The TFT arrangement structure can reduce the space of the circuit arrangement to increase the aperture ratio of the display panel and satisfy the demands of the narrow frame and high resolution to the display panel.
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