Three-dimensional memory device having passive devices at a buried source line level and method of making thereof
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United States of America Patent
Stats
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Jan 23, 2018
Issued Date -
N/A
app pub date -
Jan 30, 2017
filing date -
Nov 30, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.
First Claim
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Cited Art Landscape
Patent Citation Ranking
- 70 Citation Count
- H01L Class
- 99.22 % this patent is cited more than
- 7 Age
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