Three dimensional NAND device with channel located on three sides of lower select gate and method of making thereof
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United States of America Patent
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Jan 23, 2018
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N/A
app pub date -
Jun 27, 2016
filing date -
Dec 19, 2013
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Abstract
A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.
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