Semiconductor package including planar stacked semiconductor chips
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United States of America Patent
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Jan 23, 2018
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N/A
app pub date -
Jan 13, 2016
filing date -
Aug 3, 2015
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Abstract
A semiconductor package may be provided. A semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip and a second semiconductor chip which are disposed adjacent to each other over a first surface of the substrate. The semiconductor package may include first bonding wires which electrically couple the first semiconductor chip and the substrate. The semiconductor package may include an insulation adhesive which is interposed between the second semiconductor chip and the substrate. The first bonding wires may be disposed to pass through the insulation adhesive and electrically couple the first semiconductor chip and the substrate.
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