Interlevel conductor pre-fill utilizing selective barrier deposition

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United States of America Patent

PATENT NO 9875968
SERIAL NO

15442307

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Abstract

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A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

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Patent Owner(s)

Patent OwnerAddress
LAM RESEARCH CORPORATIONFREMONT CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ashtiani, Kaihan San Jose, US 19 1996
Dordi, Yezdi Palo Alto, US 117 2819
Kolics, Artur Dublin, US 75 1602
Lee, William T Dublin, US 17 641
Nalla, Praveen Fremont, US 15 102
Van, Cleemput Patrick A San Jose, US 57 4102
Wong, Derek San Jose, US 19 63
Zhao, Larry Lake Oswego, US 31 707

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