Method for singulating packaged integrated circuits and resulting structures

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United States of America Patent

PATENT NO 9875913
SERIAL NO

14067644

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Abstract

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A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through a top portion of the molding compound using a first beveled saw blade, while leaving a bottom portion of the molding compound remaining. The method further includes sawing through the bottom portion of the molding compound and the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the first saw blade. The resulting structure is within the scope of the present disclosure.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYNO 8 LI-HSIN RD 6 SCIENCE-BASED INDUSTRIAL PARK HSIN-CHU 300-77

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Liu, Ming-Kai New Taipei, TW 52 345
Wang, Yen-Ping Hemei Township, TW 89 452
Wu, Kai-Chiang Hsin-Chu, TW 189 1064

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