Methods and apparatuses including an asymmetric assist device
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United States of America Patent
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Jan 23, 2018
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N/A
app pub date -
Feb 3, 2014
filing date -
Feb 3, 2014
priority date (Note) -
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Abstract
Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.
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