3D NAND semiconductor device for erasing groups of bit lines
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United States of America Patent
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Jan 23, 2018
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N/A
app pub date -
Apr 21, 2015
filing date -
Nov 19, 2014
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Abstract
A semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a substrate and commonly connected to a common source line coupled to the substrate. The semiconductor device may include an operation circuit configured to perform an operation on memory cells included in the memory strings. The bit lines may be classified into a plurality of groups. The operation circuit may be configured to apply a voltage to bit lines of a selected group and set the common source line to a voltage level for the operation.
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