Memory architecture and cell design employing two access transistors
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United States of America Patent
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Jan 23, 2018
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May 14, 2014
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May 18, 2006
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Abstract
Some embodiments include an improved memory array architecture and memory cell design. In one of such embodiments, a memory cell may comprise a memory element to store a logic state and two access transistors coupled to the memory element to access the logic state of the memory element. Other embodiments are described.
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