Low-power 5T SRAM with improved stability and reduced bitcell size
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United States of America Patent
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Jan 23, 2018
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app pub date -
Mar 25, 2010
filing date -
Mar 25, 2010
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Abstract
A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.
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