Semiconductor device including a clock adjustment circuit
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United States of America Patent
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Jan 23, 2018
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N/A
app pub date -
Nov 26, 2014
filing date -
Nov 28, 2013
priority date (Note) -
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Abstract
Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.
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