Semiconductor memory device and method for operating the same
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United States of America Patent
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Jan 23, 2018
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app pub date -
Nov 20, 2014
filing date -
Jun 30, 2014
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Abstract
A semiconductor memory device includes: an enable signal generation portion suitable for generating a data output enable signal activated at a predetermined first moment corresponding to column address strobe (CAS) latency based on a read command, a strobe signal generation portion suitable for generating a data strobe signal which has a preamble section until the data output enable signal is activated from a predetermined second moment ahead of the first moment based on the read command and toggles based on a source clock during an activated section of the data output enable signal, and a data output portion suitable for outputting internal data in synchronization with the data strobe signal during the activated section of the data output enable signal.
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