Timing violation resilient asynchronous template

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9875327
APP PUB NO 20160154905A1
SERIAL NO

15016059

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Abstract

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An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.

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Patent Owner(s)

Patent OwnerAddress
UNIVERSITY OF SOUTHERN CALIFORNIA1150 S OLIVE ST SUITE 2300 LOS ANGELES CA 90015

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beerel, Peter A Encino, US 14 225
Breuer, Melvin Encino, US 2 24
Cheng, Benmao Qindao, CN 2 24
Hand, Dylan Bronx, US 2 24

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