Methods, apparatus, instructions and logic to provide vector packed histogram functionality
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Jan 23, 2018
Issued Date -
N/A
app pub date -
Jun 26, 2015
filing date -
Jun 26, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Instructions and logic provide SIMD vector packed histogram functionality. Some processor embodiments include first and second registers storing, in each of a plurality of data fields of a register lane portion, corresponding elements of a first and of a second data type, respectively. A decode stage decodes an instruction for SIMD vector packed histograms. One or more execution units, compare each element of the first data type, in the first register lane portion, with a range specified by the instruction. For any elements of the first register portion in said range, corresponding elements of the second data type, from the second register portion, are added into one of a plurality data fields of a destination register lane portion, selected according to the value of its corresponding element of the first data type, to generate packed weighted histograms for each destination register lane portion.
First Claim
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Family
International Classification(s)
- 2015 Application Filing Year
- G06F Class
- 57200 Applications Filed
- 45873 Patents Issued To-Date
- 80.20 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- G06F Class
- 0 % this patent is cited more than
- 7 Age
Maintenance Fees
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|---|---|---|---|---|
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