Memory device for performing error correction code operation and redundancy repair operation
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United States of America Patent
Stats
-
Jan 23, 2018
Issued Date -
N/A
app pub date -
Dec 7, 2016
filing date -
Apr 19, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2016 Application Filing Year
- G06F Class
- 60255 Applications Filed
- 46180 Patents Issued To-Date
- 76.65 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 2 Citation Count
- G06F Class
- 20.77 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 23, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 23, 2029 |
