Method and apparatus for a zero voltage processor sleep state
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United States of America Patent
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Jan 23, 2018
Issued Date -
N/A
app pub date -
Dec 11, 2015
filing date -
Dec 30, 2005
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
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International Classification(s)
- 2015 Application Filing Year
- G06F Class
- 57200 Applications Filed
- 45873 Patents Issued To-Date
- 80.20 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- G06F Class
- 0 % this patent is cited more than
- 7 Age
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