Self-biased multiple cascode current mirror circuit
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United States of America Patent
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Jan 23, 2018
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app pub date -
May 27, 2015
filing date -
May 27, 2015
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Abstract
A self-biased cascode current mirror/scaler circuit can include a bias FET biased with an input current to generate a gate-source voltage, which can be divided by a bias circuit into a first voltage component (e.g., at a threshold voltage) and a second voltage component (at a FET drain-source saturation voltage or edge of saturation voltage). An input FET of the current mirror/scaler circuit can receive approximately the input current or a function thereof. A gate of the input FET can be biased at the first voltage component in sum with a FET drain-source saturation voltage or edge of saturation voltage of the input FET. A gate of the output FET can be connected to the gate of the input FET. A gate of a cascode FET in series with the output FET can be biased at the first voltage component in sum with the second voltage component in sum with the FET drain-source saturation voltage or edge of saturation voltage of the input FET. Multiple cascode FETs, multiple output stages, high frequency bypass capacitors, and lowpass filters are also described.
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