Layout decomposition methods and systems

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United States of America Patent

PATENT NO 9874810
SERIAL NO

15135041

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Abstract

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A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.

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Patent Owner(s)

Patent OwnerAddress
SAMSUNG ELECTRONICS CO LTDGYEONGGI DO SOUTH KOREA GYEONGGI-DO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hwang, Sung-Wook Dongmyeong-myeon, KR 37 385
Jung, Ji-Young Hwaseong-si, KR 16 43
Kang, Dae-Kwon Yongin-si, KR 8 39
Kim, Dong-Gyun Seoul, KR 22 144
Yang, Jae-Seok Hwaseong-si, KR 21 166

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