Clock recovery method and clock recovery arrangement for coherent polarization multiplex receivers
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United States of America Patent
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Jan 16, 2018
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app pub date -
Sep 28, 2016
filing date -
Feb 5, 2010
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Abstract
Component signal values are derived from component signals and fed to at least one fixed equalizer which generates equalizer output signals. The signals are fed to phase error detectors generating phase error signals. The phase error signals are combined with further phase error signals derived by further error detectors receiving signal values from further equalizers and/or the component signal values directly from sample units.
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