Methods and apparatus for continuous current limiting for FETS in high inductive load systems
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 16, 2018
Issued Date -
N/A
app pub date -
Jun 29, 2016
filing date -
Jun 29, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An apparatus includes a FET device having a drain terminal, source terminal and a gate terminal; a first supply voltage coupled to the drain terminal of the FET; an output terminal coupled to the source terminal of the FET; a bias current supply coupled to the gate terminal of the FET; a second supply voltage coupled to the gate terminal of the FET; a current sensing circuit coupled to output a sense current proportional to the current flowing through the FET; a current limit comparator coupled to the sense current and comparing the sense current to a predetermined limit current; a pull down current circuit coupled to remove current from the gate terminal of the FET; a current time derivative circuit coupled to the sense current and outputting a sense rate current; and a circuit coupled to receive the sense rate current and coupled to the bias current supply.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully