Dual strained nanosheet CMOS and methods for fabricating
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United States of America Patent
Stats
-
Jan 16, 2018
Issued Date -
N/A
app pub date -
Mar 31, 2017
filing date -
Mar 31, 2017
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method includes: growing a lattice of alternating sheets of tensile strained silicon and relaxed silicon-germanium on a substrate; isolating a first portion of the lattice from a second portion of the lattice; forming source regions and drain regions on each of the first portion of the lattice and the second portion of the lattice; forming a first gate opening in the first portion of the lattice and a second gate opening in the second portion of the lattice; selectively removing the sheets of relaxed silicon-germanium from under the second gate opening in the second portion of the lattice; selectively removing portions of the sheets of tensile strained silicon from under the first gate opening in the first portion of the lattice; and increasing a germanium content in the relaxed silicon-germanium layers under the first gate opening in the first portion of the lattice.
First Claim
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Family
International Classification(s)
- 2017 Application Filing Year
- H01L Class
- 30754 Applications Filed
- 25260 Patents Issued To-Date
- 82.14 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 23 Citation Count
- H01L Class
- 95.06 % this patent is cited more than
- 7 Age
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