Semiconductor device including fin structures and manufacturing method thereof
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 16, 2018
Issued Date -
N/A
app pub date -
Oct 4, 2016
filing date -
Sep 4, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A semiconductor device includes device areas where a Fin FET is disposed and a non-device area disposed between the device areas, which includes a dummy structure. The Fin FET includes a fin structure having a well region including a first semiconductor layer, a stressor region including a second semiconductor layer and a channel region including a third semiconductor layer; an isolation region in which the well region is embedded, and from which at least an upper port of the channel region is exposed; a gate structure disposed over a part of the fin structure. The dummy structure in the non-device area includes a first dummy layer formed over the first semiconductor layer and made of a different material from the stressor region, and a second dummy layer formed over the first dummy layer and made of a different material from the channel region.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully