Back-end-of-line (BEOL) interconnect structure
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United States of America Patent
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Jan 16, 2018
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app pub date -
Jul 13, 2015
filing date -
Jul 16, 2013
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Abstract
A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer, with the dielectric layer having a recess therein. A silicon (Si) layer is deposited in the recess. An interconnect is formed by providing a barrier layer and a conductive layer in the recess over the Si layer. The Si layer has a density that prevents or substantially prevents the barrier layer from moving away from the conductive layer and towards the dielectric layer during subsequent processing of the interconnect structure.
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