SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING A POST PACKAGE REPAIR OPERATION AND OPERATING METHOD THEREOF
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United States of America Patent
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app pub date -
Feb 7, 2017
filing date -
Jul 18, 2016
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Abstract
A semiconductor memory device includes a fuse array circuit including a row fuse region and a column fuse region, and suitable for outputting fuse information from row fuse sets and from column fuse sets and outputting programmed row and column addresses as row and column fail data, during a boot-up operation; a fuse array control circuit suitable for storing a fail address based on a fail cell information during a repair operation, searching unused fuse sets to from the row fuse region and the column fuse region based on the fuse information during the boot-up operation, and controlling the fail address to be programmed in the unused fuse sets during a rupture operation; and a row and column redundancy circuit suitable for performing a row or column redundancy operation in correspondence to the row and column fail data.
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