Techniques and architecture for improved vertex processing

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United States of America Patent

PATENT NO 9870640
SERIAL NO

14961755

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Abstract

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An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATIONCALIFORNIA USA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Foley, Tim Concord, US 6 27
Sathe, Rahul P Emeryville, US 27 274

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