Method and apparatus for integrated circuit mask patterning
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United States of America Patent
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Jan 16, 2018
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Nov 23, 2015
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Aug 1, 2013
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Abstract
Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
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