Method for automatically generating a netlist of an FPGA program
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United States of America Patent
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Jan 16, 2018
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app pub date -
May 13, 2015
filing date -
May 13, 2014
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Abstract
A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build.
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