Systems, apparatuses, and methods for performing vector packed compression and repeat
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United States of America Patent
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Jan 16, 2018
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app pub date -
Dec 23, 2011
filing date -
Dec 23, 2011
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Abstract
Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed compression and repeat in response to a single vector packed compression and repeat instruction that includes a first and second source vector register operand, a destination vector register operand, and an opcode are described.
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