Instruction and logic for reducing data cache evictions in an out-of-order processor
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United States of America Patent
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Jan 16, 2018
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app pub date -
Mar 28, 2014
filing date -
Mar 28, 2014
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Abstract
A processor includes a resource scheduler, a dispatcher, and a memory execution unit. The memory execution unit includes logic to identify an executed, unretired store operation in a memory ordered buffer, determine that the store operation is speculative, determine whether an associated cache line in a data cache is non-speculative, and determine whether to block a write of the store operation results to the data cache based upon the determination that the store operation is speculative and a determination that the associated cache line is non-speculative.
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