Address collision avoidance in a memory device
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United States of America Patent
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Jan 16, 2018
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N/A
app pub date -
Sep 11, 2015
filing date -
Sep 11, 2015
priority date (Note) -
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Abstract
Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.
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