Memory device of adaptively calibrating timing margin and integrated circuit including the same
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United States of America Patent
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Jan 16, 2018
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N/A
app pub date -
Feb 2, 2015
filing date -
Apr 4, 2014
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Abstract
An integrated circuit, a method of controlling an operation timing of a memory device, an application processor, and a power manager are provided. The application processor includes: a power manager configured to determine a first operating power level, from among a plurality of operating power levels, to determine a first timing margin corresponding to the first operating power level, to generate a first gray code signal indicating the first timing margin, and to output the first gray code signal; and a first memory device configured to adjust an operation timing according to the first timing margin indicated by the first gray code signal, wherein the power manager is configured to provide the first operating power level to the first memory device.
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