Optimized solder pads for solder induced alignment of opto-electronic chips
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United States of America Patent
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Jan 16, 2018
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N/A
app pub date -
Oct 25, 2016
filing date -
Nov 20, 2015
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Abstract
A technique relates to assembling a multi-chip system. A first chip stack element having two major surfaces and a first solder pad, a first vertical stop, a first lateral stop and a first waveguiding element is provided. A second chip stack element having two major surfaces and including a second solder pad, a flow resistor connected to the second solder pad, a second vertical stop, a second lateral stop, a reservoir pad connected to the flow resistor, and a second waveguiding element is provided. A solder material is plated to form a plated solder pad. A technique includes pre-aligning the first chip stack element and the second chip stack element, raising the temperature to a temperature above the melting temperature of the solder material, and flowing solder through the flow resistor. Aspects include aligning the first and second waveguiding elements and cooling the connected assembly to re-solidify the solder material.
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