Scan test architecture and method for scan testing
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United States of America Patent
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Jan 16, 2018
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app pub date -
Sep 30, 2015
filing date -
Sep 30, 2015
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Abstract
A circuit and a method for testing for faults in a circuit path. The circuit comprises a memory, a collar flop connected in parallel with the memory, and a feedback path in communication with the output of the memory and the input of the collar flop. The method comprises applying a fault test vector to logic in the circuit path to produce a fault test vector response, propagating the vector or the response through a memory in the circuit path, and capturing the response in a collar flop.
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