Test pad structure, a pad structure for inspecting a semiconductor chip and a wiring substrate for a tape packaging having the same
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United States of America Patent
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Jan 16, 2018
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app pub date -
Jul 25, 2016
filing date -
Jun 25, 2008
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Abstract
A test pad structure includes a plurality of test pads and a plurality of connection leads. The test pads are sequentially arranged from a wiring pattern on a substrate and in rows parallel with one another. The test pads include first and second groups of test pads, the first group having at least one pad and the second group having at least two pads. The connection leads extend from end portions of the wiring pattern to be connected to the test pads. The connection leads include at least one inner lead passing between the at least two pads of the second group and arranged in a first row closest to the first group. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group arranged in a second row next to the first row.
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