Selective segment via plating process and structure
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United States of America Patent
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Jan 9, 2018
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N/A
app pub date -
Aug 24, 2015
filing date -
Mar 19, 2015
priority date (Note) -
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Abstract
A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.
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