Latch circuit with isolated input and/or output
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United States of America Patent
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Jan 9, 2018
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N/A
app pub date -
Jun 16, 2016
filing date -
Jun 16, 2016
priority date (Note) -
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Abstract
A latch circuit providing isolated input current paths includes a pair of input transistors that receive a differential input signal. A plurality of steering transistors receive a portion of a differential clock signal. The latch circuit includes a positive output node and a negative output node. A first bypass input current path is associated with the first input transistor and is electrically isolated from the positive output node and the negative output node. A second bypass input current path associated with the second input transistor is also electrically isolated from the positive output node and the negative output node. In a latched state, the clock signal is operative to selectively bias the plurality of steering transistors such that current is steered to one of the first input current path or the second input current path, thereby being isolated from the output nodes.
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